| |
ISTC2002-SEPTEMBER 11-14, 2002, TOKYO, JAPAN |
| |
|
|
CONFEREENCE PLENARY SPEAKER |
| |
 |
Dr. Karen H. Brown
Director of National Institute of Standards and Technology (NIST)
"Technologies for the Future" |
|
| |
CONFERENCE KEYNOTE SPEAKERS |
|
Dr. Tsugio Makimoto,
Corporate Advisor & CTO/Semiconductor Network Company, SONY Corporation
"The Impact of The Second Wave of Digital Revolution"
Dr. Frank Wen,
Executive Board Director and President of UMC
"Semiconductor Market Outlook and Technology Challenges - A Foundry Perspective"
|
|
CONFERENCE REGISTRATION |
|
|
Advance Registration |
On-Site |
| Member |
US$300 |
US$350 |
| Member |
|
Yen 40,000 (including Banquet) |
| Student |
US$150 |
US$200 |
| Student |
|
Yen 20,000 (not including Banquet) |
| Conference Banquet |
US$50 |
US$60/Yen6,000 |
|
|
Completed Registration Forms using block capitals and return to the following address along with payment. The registration form and payment MUST be received by April 30, 2001, to qualify for the advance rates. Make check or money orders payable to The Electrochemical Society, Inc. Payments must be made in U.S. funds drawn on a U.S. Bank. MasterCard or VISA are also accepted (not American Express).
Attendees prepaying by credit card may send their Advance Registration Forms to the Society Headquarters Office by Fax: 609.737.2743. If you send your Advance Registration Form by FAX, please do not send another copy by mail, as this may result in duplicate charges. All Advance Registrations will be confirmed by mail.
The Electrochemical Society,Inc., 65 South Main Street, Pennington, New Jersey 08534-2839 USA
Tel: 609.737.1902 Fax: 609.737.2743 E-mail: ecs@electrochem.org
|
|
CONFERENCE PROGRAM SCHEDULE |
|
| Sept. 12, 2002 (AM) |
|
| 8:00 am - 9:00 am |
Registration |
|
| 9:00 am - 9:20 am |
Welcome Address |
Dr. Ming Yang/Prof. M. Koyanagi |
| 9:20 am - 10:10 am |
Plenary Speech: "Technologies for the Future" |
Dr. Karen H. Brown |
| 10:10 am - 11:00am |
Keynote Speech: "The Impact of The Second Wave of Digital Revolution" |
Dr. Tsugio Makimoto |
| 11:00 am - 11:50am |
Keynote Speech: "Semiconductor Market Outlook and Technology Challenges - A Foundry Perspective" |
Dr. Frank Wen |
| Sept. 12, 2002 (PM) |
|
Session Chairs |
| 14:00 - 16:30 |
Patterning Process Technologies: Litho and Plasma Etching/Damage/Diagnostics |
W. Milne and M. Engelhardt (Sapphire Room) |
| 13:50 - 16:20 |
Device Technologies: Memory, FET, and TFT/LED |
S. Kawamura and N. Koshida (Star Ruby Room) |
| 14:00 - 16:20 |
Front End Process Technologies: Doping/II/Anneal and SIO2 Films |
A. Toriumi and H. Kurino (Emerald Room) |
| 19:00 - 21:00 |
Conference Banquet |
| Sept. 13, 2002 (AM) |
|
| 9:00 - 12:30 |
Back End Process Technologies: Copper Deposition/Integration/Reliability and CMP |
K. Masu and S. Samukawa (Star Ruby Room) |
| 9:00 - 12:00 |
Device Technologies: Silicon Nano Device and CMOS |
S. Takagi and T. Hiramoto (Sapphire Room) |
| 9:00 - 12:10 |
Packaging Technologies: Optoelectronic Packaging and Solder Bumps |
M. Bonkohara and A. Dohoya (Emerald Room) |
| Sept. 13, 2002 (PM) |
|
| 14:00 - 16:30 |
Back End Process Technologies: Thin Films and Low-k Dielectrics |
G.S. Mathad and S. Wickramanayaka (Star Ruby Room) |
| 14:00 - 16:30 |
Front End Processes: Epitaxial Silicon, STI, and High-k Films |
H. Iwai and N. Inoue (Sapphire Room) |
| 14:00 - 18:20 |
Packaging Technologies: Flip Chip and 3-D Assemblies |
T. Suga and M. Kada (Emerald Room) |
| Sept. 14, 2002 (AM) |
|
| 9:00 - 12:00 |
Poster Session |
S. Okazaki and B. Mizuno (Sapphire Room) |
|
|
THE CONFERENCE |
|
The 2nd ECS International Semiconductor Technology Conference - 2002 Japan, sponsored by the Electrochemical Society and Japan Society of Applied Physics, is organized with the intention of providing a forum for the presenting and discussion of the latest developments in silicon technology and related fields. Last year ECS sponsored the 1st ECS International Semiconductor Technology Conference hold in Shanghai, China. Dr. Jack Kilby, the year 2000 Nobel Prize Winner and integrated circuit inventor, was our conference plenary speaker.
Mr. David Wang, senior vice President of Applied Materials, delivered his keynote speech of "Semiconductor Industry Trends, Future Growth and Opportunities" and Dr. Simon Sze, National Academy of Engineering, delivered his keynote speech of "Microelectronic Technology: Challenges in the 21st Century". Also we have many famous scientists and engineers attended that meeting.
 |
This year's conference we will bring you many famous scientists too and also we have added packaging technology symposium in the conference. The Conference is also aimed at providing a forum for synergistic interactions among those working in semiconductor R&D, production, and equipment. It is also designed for those who want to learn state-of-the-art process technologies and manufacturing limitations. |
Publication of a proceedings volume is planned. Papers published in a proceedings volume may also be submitted to the JOURNAL, but must be received no later than six months after the date of the symposium at which the paper was presented. The new abstract template is available from the Society Headquarters (http://www.electrochem.org). The Abstracts should be sent to the ECS Society Headquarters by May 3, 2002. Full papers for the proceedings volume are due at the conference.
|
|
|
|
T. Endoh, Tohoku University.
New Stacked-Surrounding Gate Trsansistor (S-SGT) Structured Cell for Future Ultra High Density Flash Memory.
D. Garner, Univesrsity College London.
Technologies for Power Integrated Circuits.
T. Hiramoto, University of Tokyo.
Quantum Mechanical Effects in Nano-Scale Narrow Channel n-Type and p-Type MOSFETs.
S. Inaba, Toshiba Corp.
35 nm Gate Length CMOS Technology with Very Thin Gate Dielectrics and Ni-Salicide.
H. Ishiwara, Tokyo Institute of Technology.
Recent Progress of Materials and Device Structures in Ferroelectric Memories.
H. Ito, Applied Materials Japan.
Ion Implantation Technology for Semiconductors.
T. Itoh, University of Tokyo.
Application of Surface Activated Bonding to MEMS Packaging.
Y. Kiyota, Hitachi, Ltd.
SiGe HBT Technology Using HCl-free Selective Epitaxial Growth by LPCVD.
K. Kondo, Okayama University,
Electrodeposition Technology for Semiconductor and Semiconductor Packaging.
T. Kuroi, Mitsubishi Electric Corp.
Challenges for Isolation Scaling.
O. Mikami, Tokai University.
Optical Surface Mount Technology Based on Optical Pin.
B. Mizuno, Matsushita Electric Corp.
Ultra Shallow Junction Technology.
T. Mizuno, ASET-MIRAI
Advanced CMOS Technology Using Strained-SOI Structures.
J. Murota, Tohoku University.
SiGe Epitaxial CVD Technology for Si-Based Ultra-small Devices.
M. Nakano, Sharp Corp.,
Elevated Drain Fabrication Method using Poly-Si for Ultra Shallow Junction.
A. Nathan, University of Waterloo.
Amorphous Silicon TFT Circuit Integration.
S. Oda, Tokyo Institute of Technology.
Single Electron and Ballistic Transport in Silicon Nano Devices.
T. Osaka, Waseda University.
All-Wet Barrier Layer Fabricating Process on SiO2 for ULSI Copper Interconnection.
K. Prasad, Nanyang Technological Unioversity.
Impact of Copper Diffusion in Si, SiO2 and Low-k Materials on the Performance of CMOS Devices.
D. Pribat , Thales R&T.
Aligned Carbon Nanotubes for Parallel E-Beam Lithography Applications.
T. Yamamoto, Fujitsu Laboratories, Ltd.
Ultra Shallow Junction Profile for Sub-50 nm MOSFETs Using Laser Thermal Process.
|
|
PROGRAM OUTLINE |
|
Devices.
logic devices to include microprocessors (MPUs), ASICs, CMOS, BiCMOS, embedded memory devices to include conventional DRAMs, DRAMs with high-k and ferro-electric materials for storage node capacitors, nonvolatile memories (NVMs) with ferr-oelectric (FeRAM) and ferromagnetic materials (MRAM), and flash memory devices.
optoelectronic devices, high speed III- IV devices, high power LEDs and lasers, high frequency transistors, cold cathode and high power devices.
device physics, reliability, characterization, and applications.
Front End Processes and Integration.
trends in < 100nm technologies; front end process integration to include gate/gate dielectric for scaled technologies, alternatives to poly-silicon, ultra-thin nitride barriers; high-k gates, new gate structures, and gate metals.
rapid thermal processes and integration issues such as pattern effects, annealing ambients, ultra shallow junction formation, shallow junctions & salicides.
trench & stacked capacitors for DRAMs, isolation schemes & processes: shallow trench isolation, limits of isolation schemes, mechanical stress, reliability and yield issues.
Back End Processes and Integration.
advanced metallization to include copper deposition, alloying aspects, copper integration in ULSI; new contact metals and vias.
lowk inter-level dielectric film patterning processes and related integration issues such as k-value degradation, resist poisoning, CD control, adhesion.
barrier metal deposition (e.g. CVD, ionized metal plasma, collimated deposition), diffusion behavior, and related integration issues.
scaling of ultra-thin functional films (barrier, seed layers) used in interconnects.
CMP processes & control for damascene structures and integration issues relating to copper and low-k films.
Patterning Processes.
lithography systems for < 100 nm ground rules to include EUV, EPL and other advanced exposure tools, resist systems, processes, and metrology.
plasma etching processes for high-k films, noble metals for FeRAMs & MRAMs; challenges of anisotropy, selectivity, and CD control; process diagnostics and control; device damage & control; new plasma sources/reactors, novel processes.
Manufacturing Methods.
new manufacturing architectures, factory controls (AEC/APC), yield & cost management; issues related to 300 mm factories and processing, future projections.
Packaging Technologies.
system-on-chip architecture & integration, 3D packaging like flip chip bonding.
wafer level package and CSP, very high frequency packaging designs, heat dissipation control.
noise control, EMI, EMC, fine pitch multi-layered electronic circuitry, opto-electronic hybrid circuitry, super-connections, advanced multi-functional interposer & new active and passive hybrid boards, MCM & microwave circuit modules (MMCM), wafer level burn-in & testing, optical connector & ferrules, optical wave guides, new ceramic, organic, and mixed circuit materials, fine pitch packaging process & assembly and equipment, new encapsulation adhesives, bonding material and new processes & equipment, testing and burn-in equipment, KGD.
|
|
THE VENUE |
|
Approximately halfway along the long and arc-shaped archipelago of Japan, spreading over the Kanto Plain and facing the Pacific Ocean, there is the megalopolis of Tokyo. The city presents a complex urban landscape, laced with layer upon layer of railways and highways with a mighty conglomeration of buildings in between. But if Tokyo appears immense and daunting from above, alight for a while in its midst, and you will see that down on the ground it is well organized and highly civilized on a human scale.
Tokyo is clean and safe, easy to get around, and to get things done. The low crime rate is famous, and the efficiency of the city's public transport legendary. |
|
|
 |
Computerized systems keep the city functioning smoothly; shopping is easy, and information is on tap from any source in the world via printed media or on screen . |
|
|
Accomoodations |
|
Diamond Hotel is located in Tokyo and has 500 guest rooms. The hotel equipped with balls room and conference rooms. There are also Chinese, Japanese and Western Restaurants in the hotel. For more information please visit Hotel webpage www.diamond-hotel.co.jp
Please fill out the hotel reservation form and fax to Diamond before August 10, 2002 to receive ISTC2002 conference rate.
TEL:03-3263-2211
FAX:03-3263-2222
E-Mail: info@diamond-hotel.co.jp |
|
Travel to Tokyo |
|
Tokyo is serviced by two major airports, Narita and Haneda. All international carriers, with the exception of China Airlines, fly to and from Narita. If you can forget its inconvenient location, Narita is an excellent airport with a host of services available to the traveller willing to seek them out. The bulk of domestic air traffic goes through Haneda. Fortunately, the two airports are connected by a regular bus service.
Arriving in Tokyo by train is a simple affair. Most of the major train lines terminate at Tokyo station on the Japan Railways (JR) Yamanote line. For day trips to areas such as Kamakura, Nikko, Hakone and Yokohama, the most convenient means of transport is usually one of the private lines. There are also three shinkansen, or bullet train, lines that connect Tokyo with the rest of Japan. Buses - about the same price as trains - ply the
expressways between Tokyo and various other parts of the country. The buses will often run direct, so that you can relax instead of watching for your stop. |
|
|
|
ORGANIZERS
Conference Chairmen
Ming Yang (Chair) Texas Instruments, Inc., USA
M. Koyanagi (Chair) Tohoku University, Japan
Conference Co-Chairmen
G.S. Mathad (Co-chair) S/C Tech. Consulting, USA
M. Engelhardt (Co-chair) Infineon Technologies, AG, Germany
Executive Committee Members
Ming Yang Texas Instruments, Inc., USA
M. Koyanagi Tohoku University, Japan
G.S. Mathad S/C Tech. Consulting, USA
M. Engelhardt Infineon Technologies, AG, Germany
Bill Milne Cambridge University
Jin Jang Korea National Laboratory of TFT
H. Iwai Tokyo Inst. of Technology, Japan
S.F. Yoon Nayang Technological University
International Advisory Committee:
T. Hattori Musahi Inst. of Technology, Japan
Y. Horiike University of Tokyo, Japan
M. Matsumura Tokyo Inst. of Technology, Japan
K. Prasad Nanyang Technological Univ., Singapore
G. Bronner IBM Microelectronics, USA
Ju-Yan Xu Academician of Chinese Academy of Engineering
Dennis W. Hess Georgia Institute of Technology
M. Bonkohara Association of Super-Advanced Elecronics Technologies
Y. Yasuda Nagoya University, Japan
Technical Program Committee:
G.S. Mathad (Chair) S/C Tech. Consulting, USA
H. Iwai (Co-chair) Tokyo Inst. of Technology, Japan
A. Dohya NEC Corp., Japan
N. Inoue Osaka Prefectural University, Japan
M. Kada Sharp Corp., Japan
N. Koshida Tokyo University of Agriculture and Technology, Japan
K. Masu Tokyo Inst. of Technology, Japan
S. Okazaki ASET, Japan
S. Samukawa Tohoku University, Japan
T. Suga University of Tokyo, Japan
A. Toriumi University of Tokyo, Japan
Jeff Chinn Applied Materials, USA
S.F. Yoon Nayang Technological University
K. Rajkanan KLA-Tencor
Jian-Hui Ye Institute of Materials Research & Engineering, Singapore
L. Monastyrskii L'viv National University (Formal Russia)
Conference Administration/Secretary:
E. Brennfleck The Electrochemical Soc., Inc., USA
S. Takagi Toshiba, Japan
Japan Local Committee:
S. Kawamura AIST Chair
T. Hiramoto University of Tokyo Local Arrangement
H. Kurino Tohoku University Secretary
B. Mizuno Matsushita Finance
Sunil Wickramanayaka Anelva Publicity
Y. Suda Tokyo University of Agriculture and Technology Presentation
S. Takagi Toshiba Registration
|
|
This Conference is Co-Sponsored by IEEE and Japan ASET |
|
|
|
